Voltage converters of a non-insulated step-down type are widely used, for example, in the power-management field. The ease of use, simplicity, and excellent versatility in the various conditions of input and output voltage render the topology of a buck type one of the most widely used for this type of conversion.
FIG. 1 shows the circuit diagram of a typical buck converter 1.
In particular, a buck converter 1 includes two input terminals 10a and 10b for receiving a voltage Vin and two output terminals 12a and 12b for supplying a voltage Vout, where the output voltage is equal to or lower than the input voltage Vin.
In particular, typically, the buck converter 1 includes an electronic switch Q1 and an inductor L, which are connected (for example, directly) in series between the positive input terminal 10a and the positive output terminal 12a. Instead, the negative output terminal 12b is connected (for example, directly) to the negative input terminal, which typically represents a ground GND. Finally, a second electronic switch Q2 is connected (for example, directly) between the negative terminal 10b (or else, the negative terminal 12b) and the intermediate point between the electronic switch Q1 and the inductor L. The (high-side) switch Q1 and the (low-side) switch Q2 hence represent a half-bridge connected (for example, directly) between the terminals 10a and 10b, where the inductor L is connected (for example, directly) between the intermediate point of the half-bridge and the output terminal 12a. 
Frequently, the switches Q1 and/or Q2 are transistors, for example field-effect transistors (FETs), for instance, n-channel MOSFETs. In this case, each switch Q1/Q2 hence has associated, i.e., connected in parallel, a diode D1/D2, which typically represents the body diode of the transistor, and a capacitance C1/C2, which typically represents the parasitic output capacitance of the transistor. Frequently, the second electronic switch Q2 is also implemented just with the diode D2, where the anode is connected to the terminal 12b and the cathode is connected to the switch Q1.
In the example considered, to stabilize the output voltage Vout, the converter 1 typically includes a capacitor C connected (for example, directly) between the output terminals 12a and 12b. 
In this context, FIGS. 2a to 2f shows some waveforms of the signals of such an electronic converter, where:
FIG. 2a shows the signal DRV1 for switching the electronic switch Q1;
FIG. 2b shows the signal DRV2 for switching the second electronic switch Q2;
FIG. 2c shows the current IQ1 that traverses the electronic switch Q1;
FIG. 2d shows the voltage VS at the intermediate point between the electronic switch Q1 and the inductor L (i.e., the voltage at the second switch Q2);
FIG. 2e shows the current IL that traverses the inductor L; and
FIG. 2f shows the electrical losses PQ1 at the switch Q1.
In particular, when the electronic switch Q1 is closed at an instant t1 (ON state), the current IL in the inductor L grows linearly. The electronic switch Q2 is at the same time opened (with the diode D2 reverse biased). Instead, when the electronic switch Q1 is opened after an interval TON1 at an instant t2 (OFF state), the electronic switch Q2 is closed (with the diode D2 forward biased), and the current IL drops linearly. Finally, the switch Q1 is closed again after an interval TOFF1. In the example considered, the switch Q2 (or a similar diode) is hence closed when the switch Q1 is open, and vice versa.
The current IL can thus be used for charging the capacitor C, which supplies the voltage Vout at the terminals 12a and 12b. 
In general, the electronic converter 1 hence includes a control circuit 14 that drives switching of the switch Q1, and possibly of the switch Q2, for repeating the intervals TON1 and TOFF1 periodically.
An extremely large number of driving schemes are known for the switch Q1, and possibly for the switch Q2. These solutions have in common the possibility of regulating the output voltage Vout by regulating the duration of the interval TON1 and/or the interval TOFF1.
For instance, in many applications, the control circuit 14 generates a driving signal DRV1 for the switch Q1 (and possibly a driving signal DRV2 for the switch Q2), where the driving signal DRV1 is a PWM (Pulse-Width Modulation) signal; i.e., the duration of the switching interval TSW1=TON1+TOFF1 is constant, but the working cycle TON1/TSW1 may be variable. In this case, the control circuit 14 typically implements a PI (Proportional-Integral) or PID (Proportional-Integral-Derivative) regulator configured for varying the working cycle of the signal DRV1 in such a way as to obtain a required output voltage Vout. In this case, the various operating modes of the converter (Continuous-Conduction Mode, CCM; Discontinuous-Conduction Mode, DCM; Transition Mode, TM) are well known in the technical field.
Consequently, in the operation described previously, the switch Q1 and the switch Q2 are driven with inverted signals.
However, this presents the drawback that the switch Q1 is closed at the instant t1 when the voltage VS at the intermediate point is zero, i.e., the voltage at the switch Q1 corresponds to the input voltage Vin, thus causing electrical losses.
Furthermore, as illustrated in FIG. 2c, a nonzero current may be imposed on the switch Q1 at the instant t1 due to the flow of current that traverses the inductor IL, when the converter operates in CCM. In fact, also by opening the switch Q2, the diode D2 remains forward biased. To prevent this problem, the electronic converter 1 can hence be driven in DCM or TM, where switching of the switch Q1 occurs at the instant t1 when the current IL is zero.
However, also in this case, a current peak may present at the instant t1, since there may be required a given recovery time until the diode D2 is completely opened. However, in the meantime, the diode D2 represents a short-circuit, and the closed switch Q1 is connected directly to the input voltage Vin. These losses hence also depend upon the input voltage Vin.
Finally, the inductor L and the parasitic capacitance C1/C2 can cause additional oscillations that generate further losses.
Since these losses present at each switching of the switch Q1, the losses also increase as the frequency of switching of the switches increases.
However, power distribution is continuously evolving from various points of view, such as power density, efficiency, and cost of the solution. For instance, to meet the increasingly stringent requirements of power density it is necessary to reduce the size of the magnetic components, and to do this it is necessary to increase the operating frequency of the system. However, as explained previously, as the operating frequency increases, also the switching losses increase linearly. To satisfy these increasingly stringent requirements of high efficiency, there have hence been developed switching elements that present an increasingly high performance in terms of switching speed and figure of merit (resistance RDSon of the switch Q1 in the closed condition multiplied by the charge Qg required as long as the switch Q1 is closed).
The availability of MOSFETs with higher switching speed hence makes it possible to increase the switching frequency to reduce the magnetic components (inductances) and thus increase the power density of the conversion systems. However, the use of faster transistors requires the development of more costly technologies with a major impact on the cost of the final converter solution.
Another way to reduce or even eliminate altogether the switching losses is to get the MOSFETs to function in ZVS (Zero-Voltage Switching) conditions. For instance, with reference to a buck converter, there the document U.S. Pat. No. 8,115,460 may be cited, the contents of which are incorporated herein by way of reference.
For instance, FIG. 3 shows the circuit diagram of such a converter of a buck type commonly referred to as “ZVS buck converter”. In particular, the ZVS buck converter is constituted by the classic half-bridge Q1/Q2 of a buck converter, the inductance L, and in addition a switch QC connected in parallel to the inductor L.
FIGS. 4a to 4f once again show the signals DRV1/DRV2, the current IQ1, the voltage VS, the current IL, and the electrical losses at the switch Q, and FIG. 4g shows the additional driving signal DRVQC for the switch QC.
In particular, to get the converter to function in ZVS mode it is necessary to drive it as if it were working in DCM. Furthermore, the voltage VS at the switch Q2 should reach the input voltage Vin; i.e., the capacitance C2 associated to the switch Q2 should be charged prior to the instant t1. In particular, to charge the aforesaid output capacitance C2 of the MOSFET bridge, a negative current IL is required from the output to the intermediate point of the half-bridge.
For instance, typically, a current sensor monitors the current that traverses the switch Q2 (or alternatively the inductor L) and provides the indication that the current IL has reached a given threshold value at an instant t3. Consequently, at the instant t3, the switch Q2 is opened, and the switch QC is closed. In this way, the current in the inductance L remains substantially constant at the predefined value and is ready to charge the intermediate node of the half-bridge for the next high-side switching-on.
In particular, at the instant t4, the switch QC is opened, and the negative current supplied by the inductor L is now used for charging the capacitance C2. Consequently, by choosing the correct threshold value for the instant t3, switching of the switch Q1 at the instant t1 can occur at zero current and zero voltage.
Even though this solution uses just one inductor L, two power MOSFETs Q1 and Q2, and one parallel MOSFET QC of small dimensions, it presents various disadvantages.
For instance, one of the most evident disadvantages is that, since it practically operates in DCM, the current ripple in the inductance L is practically twice the load current. This disadvantage leads to using this converter for currents that are not very high and to using different output filter capacitances C for filtering the high current ripple at high load that flows in the inductor L.
Another disadvantage of the topology is that the switching frequency markedly depends upon the output current Iout supplied through the terminals 12a and 12b, and more precisely is inversely proportional to the current required. This behaviour may prove problematical for proper compensation of the system.
A further disadvantage is that the system cannot absorb current from the load (the so-called sink mode) if not for very limited values.